Yeonbae Chung and Taehoon Kim, "A steady-state LDMOST model based on semi-numerical regional approach",
International Journal of Emerging Technology and Advanced Engineering, Vol. 12, Issue 9, pp. 94-101, September 5, 2022.
[24]
Taehoon Kim, Sivasundar Manisankar and Yeonbae Chung, "A novel 8T cell-based subthreshold static RAM for ultra-low power platform applications",
Electronics, Vol. 9, Issue 6, pp. 1-17, June 2, 2020.
[23]
Sivasundar Manisankar and Yeonbae Chung, "P-channel logic 2 T eDRAM macro with high retention bit architecture",
International Journal of Circuit Theory and Applications, Vol. 46, No. 7, pp. 1416-1425, July 2018.
[22]
Yeonbae Chung and Hyunmyoung Kim, "A differential subthreshold SRAM cell for ultra-low voltage embedded computing applications",
International Journal of Applied Engineering Research, Vol. 12, No. 18, pp. 7998-8003, September 30, 2017.
[21]
Weijie Cheng, Hritom Das and Yeonbae Chung, "A logic-compatible embedded DRAM utilizing common-body toggled capacitive cross-talk",
Journal of Semiconductor Technology and Science, Vol. 16, No. 6, pp. 781-792, December 2016.
[20]
Sivasundar Manisankar and Yeonbae Chung, "Small-swing cross-coupled inverters based low-power embedded memory in logic CMOS technology",
International Journal of Applied Engineering Research, Vol. 11, No. 4, pp. 2749-2754, February 29, 2016.
[19]
Yeonbae Chung, Weijie Cheng and Hritom Das, "Built-in parasitic-diode-based charge injection technique enhancing data retention of gain cell DRAM",
IET Electronics Letters, Vol. 51, No. 23, pp. 1854-1855, November 5, 2015.
[18]
Yeonbae Chung, "Stability and leakage characteristics of novel conducting PMOS based 8T SRAM cell",
International Journal of Electronics, Vol. 101, No. 6, pp. 831-848, June 2014.
[17]
Weijie Cheng and Yeonbae Chung, "Bit-area efficient embedded pseudo-SRAM utilising dual-threshold hybrid 2T gain cell",
IET Circuits, Devices and Systems, Vol. 8, Issue 2, pp. 107-117, March 2014.
[16]
Y. Chung and D. -Y. Lee, "Differential-read symmetrical 8T SRAM bit-cell with enhanced data stability",
IET Electronics Letters, Vol. 46, No. 18, pp. 1258-1260, September 2, 2010.
[15]
Yeonbae Chung and Weijie Cheng,
"CMOS latch bit-cell array for low-power SRAM design",
IEICE Electronics Express, Vol. 7, No. 15, pp. 1145-1151, August 10, 2010.
[14]
Jung-Chan Lee and Yeonbae Chung, "PMOS-switching dual-path charge pump in standard twin-well CMOS technology",
International Journal of Electronics, Vol. 97, No. 3, pp. 273-283, March 2010.
[13]
Yeonbae Chung and Seung-Ho Song, "Implementation of low-voltage static RAM with enhanced data stability and circuit speed",
Microelectronics Journal, Vol. 40, No. 6, pp. 944-951, June 2009.
[12]
Jung-Hyun Kim and Yeonbae Chung, "A compact ferroelectric capacitor macro model for FRAM circuit simulation",
Integrated Ferroelectrics, Vol. 96, Issue 1, pp. 131-139, January 2008.
[11]
Yeonbae Chung and Sang-Won Shim,
"An experimental 0.8 V 256-kbit SRAM macro with boosted cell array scheme",
ETRI Journal,
Vol. 29, No. 4, pp. 457-462, August 2007.
[10]
Y. Chung and S. -W. Shim,
"Sub-1 V embedded SRAM with bit-error immune dual-boosted cell technique",
IET Electronics Letters,
Vol. 43, No. 3, pp. 157-159, February 1, 2007.
[09]
Yeonbae Chung, Jung-Hyun Kim, and Jae-Eun Yoon,
"A 2-Mb 1T1C FeRAM prototype based on PMOS-gating
cell structure", IEICE Transactions on Electronics,
Vol. E87-C, No. 10, pp. 1686-1693, October 2004.
Y. Chung, "High performance ferroelectric
memory with grounded-plate PMOS-gate cell
technology", IEE Proceedings - Circuits,
Devices and Systems, Vol. 150, No. 3, pp.
217-226, June 2003.
[06]
Y. Chung, "Experimental 128-kbit ferroelectric
memory with 1012 endurance and 10-year data
retention", IEE Proceedings - Circuits,
Devices and Systems, Vol. 149, No. 2, pp.
136-143, April 2002.
[05]
Byung-Gil Jeon, Mun-Kyu Choi, Yoonjong Song,
Seung-Kyu Oh, Yeonbae Chung, Kang-Deog Suh,
and Kinam Kim, "A 0.4-um 3.3-V 1T1C 4-Mb
nonvolatile ferroelectric RAM with fixed bitline
reference voltage scheme and data protection
circuit", IEEE Journal of Solid-State
Circuits, Vol. 35, No. 11, pp. 1690-1694,
November 2000.
[04]
Y. Chung, "LADISPICE-1.2: a nonplanar-drift
lateral DMOS transistor model and its application
to power IC TCAD", IEE Proceedings -
Circuits, Devices and Systems, Vol. 147, No.
4, pp. 219-227, August 2000.
[03]
Yeonbae Chung, Byung-Gil Jeon, and Kang-Deog
Suh, "A 3.3-V 4-Mb nonvolatile ferroelectric
RAM with selectively driven double-pulsed
plate read/write-back scheme", IEEE Journal
of Solid-State Circuits, Vol. 35, No. 5, pp.
697-704, May 2000.
[02]
Yeonbae Chung, Byung Gil Jeon, and Kang
Deog Suh, "A 3.3-V 4-Mb nonvolatile ferroelectric
RAM: novel design techniques immune to instable
cell capacitor", Journal of the Korean
Physical Society, Vol. 35, Supplementary Issue,
pp. S884-S888, December 1999.
[01]
Y. Chung, "Semi-numerical static model
for nonplanar-drift lateral DMOS transistor",
IEE Proceedings - Circuits, Devices and Systems,
Vol. 146, No. 3, pp. 139-147, June 1999.
Domestic
Journal Papers
[07]
김태훈, 정연배, "개선된 메모리 셀을 활용한 문턱전압 이하 스태틱 램 어레이 설계",
전기전자학회논문지, 제23권, 제3호, pp. 954-961, September 2019.
[06]
Yeonbae Chung, "An advanced embedded SRAM cell with expanded read/write stability and leakage reduction",
전기전자학회논문지, 제16권, 제3호, pp. 265-273, September 2012.
[05]
정연배, 김정현, "소스제어 4T 메모리 셀 기반 소신호 구동 저전력 SRAM",
전자공학회논문지 SD편, 제47권, 제3호, pp. 7-17, March 2010.
[04]
이정찬, 정연배, "상보형 전하이동 경로를 갖는 표준 CMOS 로직 공정용 고효율 전하펌프 회로",
전자공학회논문지 SD편, 제46권, 제12호, pp. 80-86, December 2009.
[03]
심상원, 정상훈, 정연배, "이중 승압 셀 바이어스 기법을 이용한 0.8-V static RAM macro 설계",
전자공학회논문지 SD편, 제44권, 제1호, pp. 28-35, January 2007.
[02]
김정현, 정연배, "PMOS
게이트 셀 기반 2.5-V, 1-Mb 강유전체 메모리 설계",
전자공학회논문지 SD편, 제42권, 제10호, pp. 1-8, October
2005.
[01]
정연배, "Grounded-Plate PMOS
게이트 강유전체 메모리 셀을 이용한 새로운 FRAM 설계기술에 관한 연구",
전자공학회논문지 SD편, 제39권, 제12호, pp. 33-44, December
2002.
International
Conference Papers
[20]
Taehoon Kim, Hyunmyoung Kim, and Yeonbae Chung,
"Design of advanced subthreshold SRAM array for ultra-low power technology", 2018 International Conference on Electrical and Electronics Engineering, pp. 329-333, May 2018.
[19]
Hyunmyoung Kim,Taehoon Kim, Sivasundar Manisankar, and Yeonbae Chung,
"Read disturb-free SRAM bit-cell for subthreshold memory applications", 2017 IEEE International Conference on Electron Devices and Solid-State Circuits, October 2017.
[18]
Sivasundar Manisankar, Hyunmyoung Kim, and
Yeonbae Chung, "A gain cell array with
retention increment design for bit-area efficient
on-chip memory applications", 2016 International Conference on Solid State Devices and Materials,
pp.751-752, September 2016.
[17]
Hritom Das, Sivasundar Manisankar, Weijie Cheng, and Yeonbae Chung,
"Experimental N-style two-transistor eDRAM in logic CMOS technology", 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 75-78, June 2015.
[16]
Weijie Cheng, Hritom Das, Huarong Zheng, Baolong Zhou, and Yeonbae Chung,
"A gain cell based embedded DRAM with fully-restoring write-back scheme", 2014 International SoC Design Conference, pp.116-117, November 2014.
[15]
Huarong Zheng, Baolong Zhou, Weijie Cheng, and Yeonbae Chung,
"A high-retention 2T embedded DRAM with cell-body toggle scheme", 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, June 2014.
[14]
Weijie Cheng, Baolong Zhou, Huarong Zheng, and Yeonbae Chung,
"Stack-transistor based differential 8T SRAM cell for embedded memory applications", 2012 IEEE International Conference on Electron Devices and Solid State Circuits, December 2012.
[13]
Weijie Cheng, Jeong-Wook Cho, and Yeonbae Chung,
"Design of logic-compatible embedded DRAM using gain memory cell", 2012 International SoC Design Conference, pp. 196-199, November 2012.
[12]
Jae-Ho Ryu, Weijie Cheng, Yong-Woon Kim, Jeong-Wook Cho, and Yeonbae Chung,
"Low-power accessless SRAM macro in logic CMOS technology", 2010 IEEE International Conference on Solid-State
and Integrated Circuit Technology, pp. 90-92, November 2010.
[11]
Jung-Chan Lee, Jin-Young Park, and Yeonbae Chung, "Power efficient charge pump circuit in standard
twin-well CMOS technology", 2008 IEEE International Conference on Electron Devices and Solid-State Circuits,
December 2008.
[10]
Seung-Ho Song, Jung-Hyun Kim, Jung-Chan Lee, and Yeonbae Chung, "Design of 256-Kb low-power
embedded SRAM", 2007 IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 313-316,
December 2007.
[09]
Jin-Young Park and Yeonbae Chung, "A low-voltage charge pump circuit with high pumping efficiency
in standard CMOS logic process", 2007 IEEE International Conference on Electron Devices and Solid-State Circuits,
pp. 317-320, December 2007.
[08]
Yeonbae Chung, Seung-Ho Song, Yoon-Joo Eom, and
Sang-Won Shim, "Low voltage SRAM with noble cell bias technique to increase static noise margin", 2'nd International Conference on Memory Technology and Design, pp. 165-168,
May 2007.
[07]
Sang-Won Shim, Yoon-Joo Eom, Seung-Ho Song, Jin-Young Park, and
Yeonbae Chung, "A 0.8-V static RAM macro utilizing dual-boosted cell bias technique", 2006 International SoC Design Conference, pp. 687-688,
October 2006.
[06]
Yeonbae Chung, Sang-Hoon Jung, Hyun-Wook Park,
Jae-Eun Yoon, and Jung-Hyun Kim, "A high efficiency FRAM design
technique with non-driven plate scheme", 2004 ICEEE, pp. 257-260,
September 2004.
[05]
Yeonbae Chung, Jung-Hyun Kim
and Jae-Eun Yoon, "Ferroelectric memory
design based on grounded-plate PMOS-gate cell
architecture", 2003 IEEE Conference on
Electron Devices and Solid-State Circuits,
pp. 55-58, December 2003.
[04]
Chikai Ohno, Hirokazu Yamazaki, Hideaki
Suzuki, Eiichi Nagai, Hisashi Miyazawa, Kaoru
Saigoh, Tatsuya Yamazaki, Yeonbae Chung, William
Kraus, Don Verhaeghe, George Argos, John Walbert,
and Sanjay Mitra, "A highly reliable
1T1C 1Mb FRAM with novel ferro-programmable
redundancy scheme", 2001 IEEE International
Solid-State Circuits Conference, pp. 36-37,
February 2001.
[03]
Byung-Gil Jeon, Mun-Kyu Choi, Yoonjong Song,
Seung-Kyu Oh, Yeonbae Chung, Kang-Deog Suh,
and Kinam Kim, "A 0.4um 3.3V 1T1C 4Mb
nonvolatile ferroelectric RAM with fixed bit-line
reference voltage scheme and data protection
circuit", 2000 IEEE International Solid-State
Circuits Conference, pp. 272-273, February
2000.
[02]
Byung-Gil Jeon, Moon-Kyu Choi, Seung-Gyu
Oh, Yeonbae Chung, Kang-Deog Suh, and Kinam
Kim, "A novel cell charge evaluation
scheme and test method for 4Mb nonvolatile
ferroelectric RAM", 6'th International
Conference on VLSI and CAD, pp. 281-284, October
1999.
[01]
Yeonbae Chung, Mun-Kyu Choi, Seung-Kyu Oh,
Byung-Gil Jeon, and Kang-Deog Suh, "A
3.3-V 4-Mb nonvolatile ferroelectric RAM with
a selectively-driven double-pulsed plate read/write-back
scheme", 1999 Symposium on VLSI Circuits
Digest of Technical Papers, pp. 97-98, June
1999.
Domestic
Conference Papers
[13]
Weijie Cheng, Baolong Zhou, Huarong Zheng, and Yeonbae Chung, "A 1.2-V 2T embedded DRAM macro in generic logic CMOS technology", 제21회 한국반도체학술대회,
pp. 403-403, February 2014.
[12]
Weijie Cheng, Jeong-Wook Cho, Yong-Woon Kim, and Yeonbae Chung, "A hybrid dual threshold 2T gain cell for embedded memory applications", 제19회 한국반도체학술대회,
pp. 228-229, February 2012.
[11]
김영훈, 조정욱, 정연배, "Subthreshold 로직 메모리 응용을 위한 0.3-V 8T SRAM bit-cell 설계", 2010년도 대한전자공학회 추계종합학술대회,
pp. 42-43, November 2010.
[10]
김용운, 청웨이지에, 정연배, "Dynamic gain 메모리 구현을 위한 1.2-V auto-refresh 회로 설계", 2010년도 대한전자공학회 추계종합학술대회,
pp. 40-41, November 2010.
[09]
이대영, 김영훈, 정연배, "저전압 SRAM 동작마진 개선을 위한 0.13um CMOS 로직 8T 메모리 bit-cell 설계", 2010년도 SoC 학술대회,
pp. 410-413, May 2010.
[08]
이승재, 류재호, 정연배, "시뮬레이션 기반 accessless 4-트랜지스터 SRAM 회로", 2009년도 대한전자공학회 추계종합학술대회,
pp. 39-40, November 2009.
[07]
김정현, 이승재, 정연배, "4T-cell based super-low standby power static RAM", 제16회 한국반도체학술대회,
pp. 410-411, February 2009.
[06]
송승호, 이정찬, 김정현, 박진영, 정연배, "Low-standby-power sub-1V SRAM macro", 제15회 한국반도체학술대회,
pp. 509-510, February 2008.
[05]
엄윤주, 송승호, 정연배,
"누설전류 감소기법을 적용한 256-Kb embedded SRAM 설계",
2006년도 대한전자공학회 추계종합학술대회,
pp. 431-434, November 2006.
[04]
박현욱, 심상원, 정연배,
"저전압 SRAM의 고속동작을 위한 전류감지 증폭기",
2005년도 대한전자공학회 추계종합학술대회,
pp. 727-730, November 2005.
[03]
정상훈, 엄윤주, 정연배,
"이중 부스팅 회로를 이용한 저전압 SRAM",
2005년도 대한전자공학회 추계종합학술대회,
pp. 647-650, November 2005.
[02]
Jung-Hyun Kim, Jae-Eun Yoon, Sang-Hoon Jung, Hyun-Wook Park,
and Yeonbae Chung, "An 128-KByte FeRAM module based on
PMOS-gating cell structure", 제12회 한국반도체학술대회,
pp. 125-126, February 2005.
[01]
Yeonbae Chung, Byung-Gil Jeon,
Seung-Kyu Oh, Mun-Kyu Choi, and Kang-Deog
Suh, "A 3.3-V 4-Mb nonvolatile ferroelectric
RAM: novel design techniques immune to instable
cell capacitor", 제6회 한국반도체학술대회 논문집, pp.
397-398, February 1999.
International
Journal Papers
